• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The method comprises 1) an embodiment of a blank (EB1) incorporating at least one electronic chip (MT, MD) between stratified insulating and / or conducting internal layers, 2) a mechanical fastening, via dielectric portions. resin prepreg (PP1, PP2, PP3), metal bar bus sections (BB1, BB2, BB3) at predetermined spaced locations on opposite high and low sides of the blank, and 3) for each of the faces opposite high and low, an interconnection by electrolytic deposition of metal layer (ME) bar bus sections fixed on the face and an electrode of the electronic chip, thus forming an electronic power circuit comprising bus bars forming dissipators thermal (BBH, BBL).
    公开号:FR3060846A1
    申请号:FR1662804
    申请日:2016-12-19
    公开日:2018-06-22
    发明作者:Friedbald Kiel
    申请人:Institut Vedecom；
    IPC主号:
    专利说明:

    Holder (s): INSTITUT VEDECOM.
    Agent (s): PEUGEOT CITROEN AUTOMOBILES SA Public limited company.
    METHOD FOR THE INTEGRATION OF POWER CHIPS AND BAR BUSES FORMING THERMAL DISSIPATORS.
    FR 3 060 846 - A1 f5 // The method comprises 1) making a blank (EB1) integrating at least one electronic chip (MT, MD) comprised between internal insulating and / or conductive laminated layers, 2) a fixing mechanical, through dielectric portions of resin prepreg (PP1, PP2, PP3), of metal bar bus sections (BB1, BB2, BB3) at predetermined spaced locations on opposite upper and lower sides of the blank, and 3) for each of the upper and lower opposite faces, an interconnection by electrolytic metal layer (ME) deposition of the bus bar sections fixed on the face in question and of an electrode of the electronic chip, thus forming a circuit power electronics comprising bus bars forming heat sinks (BB H , BB L ).
    EB1

    METHOD FOR INTEGRATING POWER CHIPS AND
    BUS BARS FORMING THERMAL DISSIPATORS [001] The invention relates generally to the field of power electronics. More particularly, the invention relates to a method for integrating power electronic chips and for interconnecting bus bars forming heat sinks in electronic power devices such as converters and power modules. The invention also relates to electronic power devices obtained by the implementation of the above-mentioned method.
    Electronic power devices, such as power converters, are very present in many fields of activity such as transport, industry, lighting, heating, etc. With the desired energy transition to renewable energy sources that produce less CO 2 emissions, power electronics are set to become more widespread and will have to respond to growing economic and technological constraints.
    Current research and development is focused on reducing costs, increasing power density, increasing reliability, reducing parasitic elements and the heat transfer of dissipated energy.
    In the current state of the art, it is usual to use so-called HDI technology, from "High Density Interconnect" in English, to increase the level of integration and reduce the size of the power circuits. HDI technology generally implemented on printed circuits called PCB, from "Printed Circuit Board" in English, is based on an optimization of the spatial layout of the components by using in particular ribbons and ceramic plates carrying a trace circuit in copper, called "lead frames", to interconnect surface mounted components or, in more advanced technology, so-called "microvias" micro-holes filled with copper to interconnect embedded components. Drilling by laser beam is used as well as various welding techniques such as for example brazing, transient liquid phase welding known as TLP welding or powder sintering of metallic nanoparticles.
    HDI technology finds its limits, however, in the face of the cost reductions that are necessary for mass production, and the increase in the level of integration and compactness. The level of integration that can be achieved is limited by the volume occupied by the interconnections with ribbons and microvias. Interconnections with tapes or cables introduce parasitic inductances which oppose higher switching or switching frequencies. However, the increase in switching frequencies is generally favorable for compactness, especially in power converters. The reduction of parasitic inductances is also necessary to reduce the heat generated, protect the circuits against potentially destructive overvoltages and improve the control of electromagnetic radiation.
    Effective cooling is necessary to maintain the temperatures of the active and passive components below critical values, to achieve thermal equilibrium and guarantee the reliability of the power circuits. The availability of silicon chips with increasingly reduced surfaces and the new power semiconductors, like silicon carbide, allow higher current densities and an increase in the cutting frequency, which allows a compactness even power circuits. But for this, the architecture of the power circuits and the technology used must ensure that the dissipated energy is extracted as close as possible to the components. It is necessary to optimize the thermal path between the heat sources made up of the components and the heat sinks made up of heat dissipation means.
    In known technologies, the heat must pass through different layers such as the solder, the copper-plated dielectric substrate, the base metal plate, the thermal interface material and the mass of the heat sink, before being transferred. in air or in coolant.
    It now appears necessary to propose a new technology for the manufacture of electronic power devices having superior heat dissipation performance and allowing better optimization with respect to the various constraints that apply.
    According to a first aspect, the invention relates to a method of integrating power electronic chips and bus bars forming heat sinks for the production of an electronic power circuit. According to the invention, the method comprises:
    - An embodiment of a blank incorporating at least one electronic chip comprised between insulating and / or conductive laminated internal layers;
    - mechanical fixing, by means of dielectric portions of resin prepreg, of sections of metal bar bus at predetermined spaced locations on opposite upper and lower faces of the blank; and
    - For each of the upper and lower opposite faces, an interconnection by electrolytic deposition of a metal layer of the sections of bar bus fixed on the face in question and of an electrode of the electronic chip, thus forming the electronic power circuit comprising bus bars forming heat sinks.
    According to a particular characteristic of the method of the invention, the production of the blank comprises a step of laminating two laminates having dielectric layers of resin prepreg comprising between them the electronic chip, and the outer faces of the laminates being formed of a metal sheet.
    According to another particular characteristic, the production of the blank includes a step of removing material by machining to produce at least one cavity in the blank and to release at least one contact face of the electronic chip.
    According to yet another particular characteristic, the production of the blank comprises a step of electrolytic deposition of a conformal layer of metal.
    According to yet another particular characteristic, the production of the blank includes an electrolytic deposition step of metal filling.
    According to yet another particular characteristic, the production of the blank comprises a step of precise definition of connection patterns by photolithography and wet etching.
    According to another aspect, the invention relates to an electronic power circuit obtained by the implementation of the method as briefly described above, the metal used for the various stages of manufacture of the method being copper.
    According to yet another aspect, the invention relates to an electronic power device comprising at least two circuits as mentioned above, a first said high circuit being stacked on a second said low circuit, the high and low circuits being mechanically and electrically linked by their respective bus bars, at least one central space for circulating coolant being located between the top and bottom circuits, and the central space for circulating coolant being formed between sections of bus bars.
    According to a particular characteristic, the device also comprises at least one top space for circulating coolant which is located in an upper part of the device, and the top space for circulating coolant being formed between sections d '' a high bar bus of the high circuit and a high dielectric layer.
    According to another particular characteristic, the device also comprises at least one bottom space for circulating coolant which is located in a lower part of the device, and the bottom space for circulating coolant being formed between sections of a low bar bus of the low circuit and a low dielectric layer.
    Other advantages and characteristics of the present invention will appear more clearly on reading the detailed description below of several particular embodiments of the invention, with reference to the accompanying drawings, in which:
    Figs. 1 to 13 are simplified sectional views showing steps of the process for integrating power electronic chips and bus bars forming heat sinks according to the invention; and Figs.14 and 15 are simplified sectional views showing first and second embodiments of an electronic power device according to the invention, with heat dissipation by air and by coolant.
    A particular embodiment of the method according to the invention is now described above in the context of the production of an electronic power device or module in the form of a switching bridge or half-bridge branch. with transistors. Conventionally, the bridge branch comprises a high transistor and a low transistor, respectively called "low side" and "high side" in English, and associated diodes. Such devices can be combined to form complete switching bridges or associated in parallel to pass the desired current.
    In general, it is used in the invention of known and well mastered manufacturing techniques of printed circuits for the integration of electronic chips. Thus, in the process according to the invention, a combination of different manufacturing techniques can be used, including lamination, photolithography, electroplating of metal and wet etching. The electroplating of metal will be used in particular for the interconnection of electronic chips and bus bars.
    Referring to Figs.1 to 13, it is now described in detail different manufacturing steps involved in the process of integrating power electronic chips and bus bar interconnection according to the invention.
    Figs. 1 and 2 show an initial step of manufacturing an LA1 laminate formed from a CD1 dielectric layer coated with a conductive metal sheet
    FC1.
    The dielectric layer CD1 is a thick sheet of prepreg 5 typically composed of a woven glass fiber dielectric coated with an epoxy-type resin and partially polymerized. The conductive metal sheet
    FC1 is typically a copper foil which is laminated on the dielectric layer CD1, as shown in Fig.2.
    In the step of FIG. 3, component chips, for example, in the form of a power transistor MT and a diode MD, are transferred to the dielectric layer CD1 of the laminate LA1 to predetermined locations. Indexing means, not shown, are used here for the placement of the chips.
    The step of Fig.4 shows the stratification of the LA1 laminate carrying the 15 MT and MD chips with another LA2 laminate obtained by the steps of Figs. 1 and 2. At this stage, the dielectric layers CD1 and CD2 are still only partially polymerized. The MT and MD chips are then sandwiched between the laminates LA1 and LA2, more precisely between the dielectric layers CD1 and
    CD2 laminates. LA1 and LA2 laminate therebetween is typically obtained by pressing and passing through the vacuum lamination furnace.
    At the outlet of the vacuum stratification furnace, in FIG. 5, there is obtained a blank EB1 in which the chips MT and MD are buried in a dielectric layer CD, completely polymerized and coming from the stratification of the layers CD1 and CD2. The copper sheets FC1 and FC2 constitute opposite upper and lower faces of the blank EB1.
    In the step of Fig.6, material removal operations by machining, for example laser, are carried out on the upper and lower faces of the blank EB1 and cavities CA1 to CA5 are carried out in two sides of the blank to release contact faces from the MT and MD chips.
    In the step of Fig.7, a conformal metal layer CF is produced on the machined upper and lower faces of the blank EB1. The CF layer is typically a copper layer produced by electrolytic deposition.
    In the step of Fig.8, an electrolytic filling deposition is carried out to completely fill the cavities CA1 to CA5 and all of the opposite upper and lower faces of the blank EB1 with copper. The top and bottom faces of the EB1 blank are then completely flat and covered with copper.
    The steps of Figs.9 and 10 relate to the precise definition of the electrical connection patterns of the MT and MD chips.
    In the step of Fig.9, a photoresist resin PS was coated on the upper and lower faces of the blank EB1 and the surface parts to be attacked in wet etching were then defined and released in the conventional manner. using a screen printing mask and exposure to ultraviolet radiation. Fig. 9 shows the blank EB1 ready for wet etching of the copper and the copper portions CP1 to CP8 to be removed.
    At the stage of FIG. 10, the copper portions CP1 to CP8 were removed by wet etching and the connection pattern is then defined with precision. The removal of the copper portions CP1 to CP8 from the cavities PD1 to PD8 which reveal portions of the underlying dielectric layer CD.
    Figs. 11 to 13 show the interconnection of top bus bars BBh and bottom BB l on the opposite top and bottom faces of the blank EB1. In addition to their usual electrical or other electrical supply functions, the top bus bars BBh and bottom bus BBl are here intended to form heat sinks installed on the opposite upper and lower faces of the blank EB1. The bus bars BB H , BB L are typically made of copper.
    As shown in Fig.11, the bus bars BB H and bottom BB L are each formed of several bus sections BB1h, BB2h, BB3h and BB1l, BB2l, BB3L which have been previously cut, for example, by mechanical machining , or possibly obtained by molding.
    Dielectric portions of prepreg PP1h, PP2h, PP3h are transferred onto corresponding faces of the bus sections BB1 H , BB2 H , BB3h intended to be pressed onto the upper face of the blank EB1. Dielectric prepreg portions PP1 | _, PP2l, PP3l are transferred onto corresponding faces of the bus sections BB1 L , BB2 L , BB3 | _ intended to be pressed onto the lower face of the blank EB1. The dielectric prepreg portions PP1 h, PP2h, PP3h and PP1 l, PP2l, PP3l are provided to fill the upper and lower cavities of the blank EB1 and adhere with the visible portions PD1 to PD4 and PD5 to PD8 of the dielectric layer. Underlying CD.
    The EB1 blank is thus sandwiched between the bus sections BB1 h, BB2h, BB3h and BB1 L , BB2 | _, BB3 | _. The bus sections BB1 h, BB2h, BB3h and BB1 l, BB2l, BB3l are pressed, with the dielectric portions of prepreg PP1h, PP2h, PP3h and PP1 | _, PP2 | _, PP3l, against the upper and lower sides of l EB1.
    The stratification of the assembly is obtained by passage through the vacuum stratification furnace. Fig. 12 shows the state of the blank EB1 with the bus sections assembled, when it has left the vacuum laminating furnace. At this stage, the bus sections have been mechanically fixed to the circuit by the complete polymerization of the dielectric portions. The dielectric circuit isolation patterns are finalized at this point.
    The step of Fig.13 is a metallization and soldering step which allows to finalize the interconnection of the conductive elements of the circuit and the bus bars forming heat sinks of the blank EB1.
    As shown in Fig.13, copper layers MEh and MEl are deposited by electrolysis on the upper and lower parts of the blank EB1.
    The copper layer ME H is deposited on the upper part of the blank EB1 is interconnects the bus sections BB1h, BB2h and BB3h of the bus bar BBh and the high faces of the transistor chips MT and corresponding MD diode, for example, to drain and cathode electrodes. The copper layer MEL l is deposited on the lower part of the blank EB1 and interconnects the bus sections
    BB1 L , BB2 l and BB3 | _ of the bus bar BB L and of the lower faces of the transistor MT and diode MD chips corresponding to source and anode electrodes.
    The method according to the invention, as described above with reference to Figs.1 to 13, authorizes the manufacture of elementary circuit bricks which can be assembled to constitute electronic devices of greater or lesser complexity of power, with a sandwich architecture. The assembly of the elementary bricks is typically carried out under a press and passing through the oven. The mechanical and electrical connections between the two bricks are made by welding. It will be noted that a parallelization of manufacturing is possible by producing the elementary circuit bricks on several manufacturing lines.
    The architecture of the elementary circuit bricks according to the invention allows direct copper contact between the heat sinks, formed of bus bars, and the electrodes of the electronic chips. Heat sinks made up of masses of copper located on either side of electronic chips and in direct contact with them allow efficient extraction of calories. In addition, the lengths of the connection conductors are minimized, which promotes the reduction of stray inductances and more compactness.
    Fig.14 shows a first embodiment EM1 of an electronic power device which is constructed by stacking two elementary bricks of circuit BChs and BCls · The device EM1 is here a branch of transistor bridge composed of two MOSFET transistors and two freewheeling diodes.
    The mechanical and electrical connection of the two stacked elementary bricks
    BChs and BCls is performed at an IP junction plane by assembling the bus bars. Assembly can be done, for example, by transient liquid phase welding called TLP or other welding techniques.
    The EM1 device is here an embodiment with mixed cooling, by coolant and by air.
    As shown in FIG. 14, the assembly of the elementary bricks BB H s and BB L s creates in the central part of the device central spaces for the circulation of coolant, here CCi and CC2. These coolant circulation spaces CC1 and CC 2 , located as close as possible to the electronic chips, are provided for the circulation under pressure of a coolant. In the upper and lower parts of the EM1 device, slot profiles of the bus bars BBh and BBl, forming heat sinks, increase the heat exchange surfaces with the surrounding air and promote the cooling of the device.
    [0048] FIG. 15 shows a second embodiment EM2 of an electronic power device. The EM2 device is provided with complete liquid cooling and is suitable for higher power applications than those of the EM1 device.
    The EM2 device differs from the EM1 device in that it is equipped with CTRLhs and CTRLls control circuits which are integrated in the upper and lower parts of the EM2 device, respectively. The control circuits CTRLhs and CTRLls are mechanically fixed and electrically isolated from the upper and lower parts of the elementary bricks BChs and BCls by dielectric layers DL H s and DLls, respectively. The circuits CTRLhs and CTRLls each comprise several laminated layers, produced according to known techniques. Active and passive components may if necessary be buried between the internal layers of the circuits CTRLhs and CTRLls, or else implanted on the surface on the circuit in a conventional manner by solder or conductive adhesive.
    As shown in FIG. 15, the integration in the upper and lower part of the device EM2 of the control circuits CTRLhs and CTRLls with the insulating dielectric layers DL H s and DL L s allows the formation of upper and lower spaces for circulation of additional coolant CH1, CH 2 and CL1, CL 2 . These additional spaces CH1, CH 2 and CL1, CL 2 located on either side of the central spaces CC1 and CC 2 allow increased cooling of the device EM2. The electronic chips are thus cooled more efficiently by the circulation of a heat transfer liquid near their upper and lower faces.
    Other embodiments of electronic power devices according to the invention are of course possible. Thus, for example, the upper part and / or the lower part of the device can be closed with simply a dielectric layer, without however establishing a control circuit at this location.
    The invention is not limited to the particular embodiments which have been described here by way of example. Those skilled in the art, depending on the applications of the invention, may make various modifications and variants which fall within the scope of the claims appended hereto.
    权利要求:
    Claims (10)
    [1" id="c-fr-0001]
    1) Process for integrating power electronic chips and bus bars forming heat sinks for the production of an electronic circuit
    5 power, characterized in that it includes:
    - an embodiment of a blank (EB1) incorporating at least one electronic chip (MT, MD) comprised between internal laminated insulating and / or conductive layers;
    - mechanical fixing, by means of dielectric portions of resin prepreg (PP1, PP2, PP3), of metal busbar sections (BB1, BB2, BB3) at predetermined spaced locations on opposite upper faces and bottom of said blank (EB1); and
    - for each of said upper and lower opposite faces, an interconnection by electrolytic deposition of metal layer (ME) of said bus bar sections
    15 (BB1, BB2, BB3) fixed on the face in question and an electrode of said electronic chip (MT, MD), thus forming said electronic power circuit comprising bus bars (BB H , BB L ) forming heat sinks.
    [2" id="c-fr-0002]
    2) Method according to claim 1, characterized in that said embodiment of the blank (EB1) comprises a step of laminating two laminates (LA1,
    LA2) having dielectric layers of resin prepreg (CD1, CD2) comprising between them said electronic chip (MT, MD), external faces of said laminates (LA1, LA2) being formed from a metal sheet (FC1, FC2 ).
    [3" id="c-fr-0003]
    3) Method according to claim 1 or 2, characterized in that said
    25 production of the blank (EB1) comprises a step of removing material by machining to produce at least one cavity (CA1 to CA5) in said blank (EB1) and to release at least one contact face of said electronic chip (MT, MD).
    [4" id="c-fr-0004]
    4) Method according to any one of claims 1 to 3, characterized in that said embodiment of the blank (EB1) comprises a step of electrolytic deposition of a conformal metal layer (CF).
    [5" id="c-fr-0005]
    5) Method according to any one of claims 1 to 4, characterized in that said embodiment of the blank (EB1) comprises a step of electrolytic deposition of metal filling.
    [6" id="c-fr-0006]
    6) Method according to any one of claims 1 to 5, characterized in that said embodiment of the blank (EB1) comprises a step of precise definition of connection patterns by photolithography and wet etching.
    [7" id="c-fr-0007]
    7) Electronic power circuit, characterized in that it is obtained by implementing the method according to any one of claims 1 to 6, the metal used for the various stages of manufacturing the process being copper.
    [8" id="c-fr-0008]
    8) Electronic power device, characterized in that it comprises at least two circuits according to claim 7, a first said high circuit (BChs) being stacked on a second said low circuit (BCls), said high and low circuits (BChs , BCls) being mechanically and electrically linked by their respective bus bars (BB H , BB L ), and in that it comprises at least one central space for circulation of coolant (CCi, CC 2 ) which is located between said top and bottom circuits (BChs, BCls), said central coolant circulation space (CCi, CC 2 ) being formed between sections (BB1 H , BB2 H , BB3 h ; BB1 l , BB2 l , BB3l) of said buses bars (BB H , BB L ).
    [9" id="c-fr-0009]
    9) Electronic power device according to claim 8, characterized in that it also comprises at least one top space for circulation of coolant (CH-ι, CH 2 ) which is located in an upper part of the device (EM2) , said upper coolant circulation space (CH-ι, CH 2 ) being formed between sections (BB1h, BB2h, BB3h) of a high bar bus (BBh) of said high circuit (BChs) and a high dielectric layer (DLhs) ·
    [10" id="c-fr-0010]
    10) Electronic power device according to claim 8 or 9, characterized in that it also comprises at least one low space for circulation of coolant (CL 1; CL 2 ) which is located in a lower part of the device (EM2 ), said low coolant circulation space (CLi, CL 2 ) being formed between sections (BB1 | _, BB2 | _, BB3l) of a low bar bus (BBl) of said low circuit (BCls) and a dielectric layer
    5 bass (DL L s)
    1/7
    FC1
    FIG. 1 CD1 LA1 FC1 t
    CD1
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    同族专利:
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
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    法律状态:
    2017-11-20| PLFP| Fee payment|Year of fee payment: 2 |
    2018-06-22| PLSC| Publication of the preliminary search report|Effective date: 20180622 |
    2019-11-20| PLFP| Fee payment|Year of fee payment: 4 |
    2020-11-20| PLFP| Fee payment|Year of fee payment: 5 |
    2021-11-18| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1662804A|FR3060846B1|2016-12-19|2016-12-19|PROCESS FOR INTEGRATING POWER CHIP AND BAR BUS FORMING THERMAL DISSIPATORS|
    FR1662804|2016-12-19|FR1662804A| FR3060846B1|2016-12-19|2016-12-19|PROCESS FOR INTEGRATING POWER CHIP AND BAR BUS FORMING THERMAL DISSIPATORS|
    EP17817810.9A| EP3555916A2|2016-12-19|2017-12-06|Method for the integration of power chips and bus-bars forming heat sinks|
    JP2019533043A| JP2020515035A|2016-12-19|2017-12-06|Method for integration of bus bars forming power chip and heat sink|
    US16/470,516| US10804183B2|2016-12-19|2017-12-06|Method for the integration of power chips and bus-bars forming heat sinks|
    PCT/FR2017/053408| WO2018115625A2|2016-12-19|2017-12-06|Method for the integration of power chips and bus-bars forming heat sinks|
    CN201780078921.1A| CN110268520A|2016-12-19|2017-12-06|Method for integrated power chip and the busbar for forming radiator|
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